Present invention embodiments relate to compression and storage of data, and more specifically, to utilizing hardware to accelerate computation and improve performance for a data processing system that stores compressed data.
The best performing software-only (i.e. able to run on arbitrary computer hardware) architectures perform computation directly on compressed data. A performance goal for such Central Processing Unit (CPU) algorithms is to achieve a rate of computation that is directly proportional to the compressed size of the data or better. Although the CPU operates directly on compressed data, and thus, the results of computation are again compressed data, the quality of compression may degrade with each successive round of computation. For example, in some cases, CPU output data may be fully decompressed, be compressed using a dictionary with duplicate entries, or be compressed using a run-length encoding (RLE) scheme where some adjacent runs have the same value. As the compression degrades, the performance of computation also degrades.
Attempting to utilize a hardware accelerator to accelerate computation by placing the accelerator in the same position in the data path as the software does not generally achieve a desired acceleration effect. For example, placing a hardware accelerator, such as a Field Programmable Gate Array (FPGA), in the same position in the datapath as the CPU, to perform the same operations as the CPU, is generally not effective because the system has been designed to maximize CPU capabilities, e.g., multi-level high performance caches, virtual memory mapping, register renaming, etc. Such operations do not map easily onto an FPGA.